Dynamic Random Access Memory (DRAM) is utilized in modern computing architectures. DRAM may provide advantages of structural simplicity, low cost and speed in comparison to alternative types of memory.
Presently, DRAM commonly utilizes memory cells having one capacitor in combination with a transistor (so-called 1T-1C memory cells), with the capacitor being coupled with a source/drain region of the transistor. One of the limitations to scalability of present 1T-1C configurations is that it is proving difficult to incorporate capacitors having sufficiently high capacitance into highly-integrated architectures. Accordingly, it would be desirable to develop new memory cell configurations suitable for incorporation into highly-integrated modern memory architectures.
Another prior art memory cell configuration, alternative to the 1T-1C configuration, is a configuration which utilizes two capacitors in combination with two transistors. Such configuration may be referred to as a 2T-2C memory cell. A 2T-2C memory cell is schematically illustrated in FIG. 1 as a memory cell 2. The two transistors of the memory cell are labeled as T1 and T2, and the two capacitors are labeled as CAP-1 and CAP-2.
A source/drain region of the first transistor T1 connects with a node of the first capacitor (CAP-1), and the other source/drain region of T1 connects with a first comparative bitline (BL-1). A gate of T1 connects with a wordline (WL). A source/drain region of the second transistor T2 connects with a node of the second capacitor (CAP-2), and the other source/drain region of T2 connects with a second comparative bitline BL-2. A gate of T2 connects with the wordline (WL). Each of the first and second capacitors (CAP-1 and CAP-2) has a node electrically coupled with a common plate (CP). The common plate may be coupled with any suitable voltage, such as a voltage within a range of from greater than or equal to ground to less than or equal to VCC (i.e., ground≤CP≤VCC). In some applications the common plate is at a voltage of about one-half VCC (i.e., about VCC/2).
The comparative bitlines BL-1 and BL-2 extend to circuitry 4 which compares electrical properties (e.g., voltage) of the two to ascertain a memory state of memory cell 2. An advantage of the 2T-2C memory cell is that a memory state may be ascertained by comparing the electrical properties of the two comparative bitlines BL-1 and BL-2 to one another. Accordingly, a reference bitline associated with prior art memory (for instance, 1T-1C memory) may be omitted.
It would be desirable to develop 2T-2C configurations suitable for incorporation into highly-integrated modern memory architectures.